IZ4406 intelligent 104-bit eeprom counter for > 20000 units with security logic features ? 104 x 1 bit organisation ? three memory areas with special characteristics (eg rom, prom, eeprom) ? maximum of 20480 count units ? special security features ? minimum of 10 4 write/erase cycles ? data retention for minimum of ten years ? contact configuration and serial interface in accordance to iso standard 7816-3 (synchronous transmission) pin definitions and functions card contact symbol function c7 i/o bidirectional data line (open drain) code entry on ?input? only for transport c3 clc clock input c2 rst control input (reset) c1 vcc supply voltage c6 n.c. not connected c5 gnd ground IZ4406 comes as an m1 wire-bonded module for embedding in plastic cards and as a die for customer packaging general description the chip contains an eeprom/prom of 88 bits, a mask rom of 16 bits and a sequencing control with security logic (cf block diagram, fig. 1 ). memory (104 bits) is divided into the following functional areas irom this area contains unalterable chip data (eg application, design status). part of the data is entered by way of a rom mask and the remainder when testing. both parts are unalterable. ii prom in this area the user can enter card data for a particular application. a control flag can be set to safeguard this area against alteration. iii prom/eeprom this area contains the count data and stores the current count in nonvolatile memory. the individual counter stages with carry can be erased (ie eeprom), only the uppermost counter stage not being erasable (ie prom). before the control flag is set, part of the eeprom area contains a secret transport code . another part serves as an error counter . function of the prom area: 1 bit: control flag 3 bits: test bits for manufacturer 4 bits: for user in the condition as supplied, the transport code and the error counter are activated. the chip can only be read (except for the transport-code area) and only the error counter can be written. following correct entry of the transport code, the entire memory can be read and areas ii and iii can be written and eeprom part of area iii can be erased.
IZ4406 after the control flag has been written, everything is readable and only area iii can be programmed, but with the following changes: - the transport code and the error counter are no longer activated. - the area of the former transport code and the error counter can be erased byte by byte with carry. - the entire area iii can be written bit by bit nb: when the control flag is written, the counter stage below it (the error counter) can be erased at the same time (see ?erasing memory byte with carry?). column decoder, 1-out-of-8 (a0-a2) address counter line decoder counter 40 bits 1-out-of-13 (a3-a6) blockable prom 40 bits manufacturer data 24 bits (ram, eeprom) chip control, security logic ieb01328 clk i/o rst gnd vcc figure 1 block diagram absolute maximum ratings parameter symbol limit values unit comments min. max. supply voltage input voltage v cc v i -0.3 -0.3 6 6 v v - - storage temperature t stg -40 125 c power dissipation p tot 50 mw -
IZ4406 operating range parameter symbol limit values unit comments min. max. supply voltage v cc 4.75 5.5 v - ambient temperature t a -35 80 c - dc characteristics parameter symbo l limit values unit test condition min. typ. max. supply supply voltage v cc 4.75 5 5.5 v - supply current i cc 1.5 3 ma - data input h-input voltage (i/o,clc,p,rst) v h 3.5 - v cc v- l-input voltage (i/o,clc,rst) v l 0-0.8v - l-input current (clk) (v h =5 v, internal pull-down) i h - - 100 a - l-input current (rst) (v h =0 v, internal pull-up) -i l - - 100 a - data output l-output current (v h =0.5 v, open drain) i l --0.5ma - h-output current (v h =5 v, open drain) i h --10 a - pulse duration rst (address reset) t r 50 - - s - rst (set r ? flag) t s 10 - - s - clc (count, h-level) t h 10 - - s - clc (count, l-level) t l 10 - - s - clc (write, h-level) t hw 5- -ms - clc (erase, h-level) t he 5- -ms - ac characteristics delay time t d1 5- - s - delay time t d2 3.5 - - s - delay time t d9 5- - s - delay time t d10 5- - s - delay time t d3 , t d4 , t d5 3.5 - - s - delay time t d6 , t d7 5- - s - delay time t d8 10 - - s -
|
